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Disadvantages of Gold-Sn Alloy (Au-Sn) Solder

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Update time : 2022-11-28 15:17:23
The disadvantage of Au80%Sn20% tin alloy is that it is more expensive, brittle, has a small elongation, and is not easy to process. In addition, due to the high melting point, it cannot be soldered with low melting point solder at the same time. It can only be used in situations where the chip can withstand a short-term higher than 300°C.
The melting point of gold-tin alloy is very sensitive to the composition near the eutectic temperature. When the weight ratio of gold is greater than 80%, the melting point increases sharply with the increase of gold. The parts to be welded often have a gold-plated layer, and the gold in the gold-plated layer diffuses into the solder during the welding process. If the gold plating layer is too thick, the pad is too thin, and the soldering time is too long, the gold diffused into the solder will increase and the melting point will rise.
1. Preformed sheet
Due to the brittle nature of gold-tin alloys, these forms of wire or sheet are difficult to process to specifications. In the process of processing, it often causes waste of materials, requires a lot of labor, and the quality is also very inconsistent.
2. Solder paste
One of the components of solder paste is flux, which is prohibited in many applications. Even where flux is available, the assembled components must be cleaned of its residue after the soldering process is complete. Moreover, although the screen printing method is simple, the surface of the film layer is rough and the edges are not smooth, which cannot meet the requirements of microelectronic products.
3. Electrochemistry
The electrochemical method ensures the precise dosage and placement of the brazing material to achieve the best quality at the lowest cost.
Au, Sn multi-layer cold-rolled AuSn20 alloy foil strips with specifications of 0.025-0.10 mm. For applications in microelectronics, optoelectronics and MEMS, pads often only need 3-5 μm, and the thinnest preform is 25 μm, and cannot meet the requirements of complex graphics, precise positioning and wafer-level bumps.
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